The resources exist; where are they? Make a small deal:"You do this and I do that ok?"

Ask some questions before giving advice were jumping in with solutions.

Bring upall of the issues that need to be addressed, all information that we produce will likelihood of any issues

A "telling" approach prevent the building of a positive relationship and makes further communication awkward. They wish you will ask them a question instead.

I want to learn how to help you best, AUO.

Can you give me an example? That's the key to humble inquiry. Then a suggestion.

How can AUO change to seize this siOG?
Start the meeting with everyone speaking from the heart before any interaction is allowed. Chair controls the process.
Start with an informal dinner meeting and begin to build relationship with them. "Why do you work for AUO ?"
What's on your mind, AUO ? So, what do you want to do? You get this reality?
You will tell me what I want to know and help me get the job done.we ever going to a relationship is going to be built here&now

What is your preference? Can you help us solve all these questions/problems?

I admit we are dependent upon you too.

No one works harder than the best to get even better. We choose you AUO as best.

Unlike LTPS, our SiOG based AMOLED is something the industry has missed out on.

For display companies who want Apple's AMOLED business, the Crystal Layer System 500 platform is a new way to manufacture AMOLED that beats LTPS and IGZO in performance and manufacturability

Having the leading marketshare will be valuable because it will lead to lower cost than your rivals. can you analyze the value?

Competitive advantage means that a business has to have a unique advantage over all of its rivals. Something valued by customers that it can do much better at a lower cost than rivals, or that it can do and the rivals can't do it all.

• What's the VALUE of working with us to Peter?
• What's the BENEFIT we are after? Battery life? Lock Apple in?
• What is the OPPORTUNITY we have if we work together?
• What is the PROBLEM that is stopping us from working together.

List the outcomes you desire, and the Behaviors you should use to promote them. List all the things to create need in the AUO folks. Push harder for your real priorities, ok?

We want to fit in with their tool flow.

You need synopsis TCAD for monte carlo simulations of device design. Simulation set.

Xerox PARC: They’ll have the wafer fab and circuit design and test facilities.

You need instrumentation to test this stuff….

Applied Materials – we need their ion implanters.

Sagar – Circuit design, sagar me and ilias work closely to get the circuit validated, tested etc. Circuit design expertise.

Intel – IP is the best, good to have, not critical. Best thing to do, it may happen in 2019.

Intermolecular – they are like Xerox PARC.

AUO is good enough. If AUO says go, we go, it’s a no brainer. Ilias has already put all the test things already. Good to go there.

Fabricate, test, extract, design.

What is the most difficult part of this process?

The uniformity of the device across the backplane. Device to device variation. Each device and its neighbor cannot differ in characteristics; defines the total functionality of the circuit and how it varies with time under illumination and when it’s powered out. The product characteristic will drift. Battery will drain fast if the process is not under control; the entire backplane will exhibit tiny useful life. Get everything solved; solve the problem of variation of time along the backplanes. Uniformity must be tight, the distribution tight, the drift of the threshold voltage is very tight; it’s better to use crystalline silicon first.

If we work together with AUO it’ll be fine. We just need to work together for 7-10 years; this kind of learning takes a lot of effort to go from one generation to another so it’s a multi-project plan. Each project may be one or two years but over time that includes different display dimensions, performance characteristics, display density. So we can design 8k 4k 12k whatever over the years. Roadmap: we’ll do all the different sizes, 4”, 5”, we do innovative design. The innovation in design that we will do is all these hybrid pixels with a focus on REDUCING POWER CONSUMPTION.

We will be a good smart design team. Like IDEO. A group at Google or Apple. We do the design, give it to you, jointly solve mfg problems, once the product is released we will split the profits. This is easy.

Can you visualize what I'm describing? Very few specialize in this.

We're not afraid of Samsung.

So partner with us to realize this vision faster.

There's a pleasant surprise. What is it?

If there's a setback, what is it? How to fix?

1. Process goal and transistor goals.

2. Q2: Ion/Ioff at room temperature 25degreesC.

3. Parameter exrtraction = we will extract low field mobility, elecrtons and holes, Vt uniformity 10%. Demonstrate VT uniformity over five inch diagonal of less than ten percent. Good target.

You must discover the picture in their head. The resources exist; where are they? Make a small deal:"You do this and I do that ok?"

Assume there's something you don't know. Make chaos your friend in negotiations.

I'm so glad to show you about AMOLED 2.0. I'm only sorry that we have only a few hours to describe how it'll whip Samsung.

Majority of investment is in place for amoled2 manufacturing. TFT array process, OLED cell process, module Ψ. Oled deposition, oled encapsulation.

Just for fun imagine we were sitting here with the completed prototype already. What would you do with it? What's next?

We have a capability that we should prove can exist with AUO within a year, and we’re ready to go with it. We don’t want to wait. Our partner, AUO, they don’t want to wait.

Our common enemy is Samsung. Can I form a vision of a relationship-with-AUO that beats them?

Samsung, Samsung, Samsung's LTPS. Wave red flag, bull charges. That's it.

I want to bring out the best in Peter.

All relationships begin with strangers. This meeting may have far reaching effects

http://metanotes.com/user/sri/AUO

Lay the groundwork for possible future actions. Intent behind each task is the key.

Test the hypothesis you have by asking.
No diagnosis until a clear cause for one.

Peter wants to be on our team because it will be a really fun project that could save AUO from Samsung and also create the best mobile screens on earth with manufacturing technology that might even be cheaper than LCD.

All forward motion comes from smart risks.

What's the most likely cause of action?

Peter understands how important our success could be for the strategic future of AUO and understands how important it is for him to join our team.

What's the probable reaction of AUO?

I'm so busy!!! I don't even know you guys!!! I'm already totally booked. I can't just spend money like that, without proof. Can AUO deliver?

The most dangerous?

We might not be able to duplicate what Sharp has done. We might not be able to build on what SHARP has done to get to the complete display for some reason.

Difficult parts?

Persuading Peter to join our team and begin working to get this prototype created. Getting our team in line to get the prototype created over here if necessary. Communicating to them back and forth. Project management.

Thickness and weight, contrast ratio, response time, view angle, power consumption, lifetime, cost advantages!

Can AUO AMOLED even afford to compete if Samsung can sell AMOLED for just 10% over the cost of LCD?

Not surprisingly the displays are the largest cost component in Apple’s new iPhones. Teardown.com estimates that they cost $41.50 (18% of the Bill Of Materials or BOM) and $51.00 (21%) for the model 6 and 6 Plus, respectively.

http://www.forbes.com/sites/chuckjones/2014/09/24/apples-iphone-6-teardown-and-other-costs-analysis/

http://www.techinsights.com/teardown.com/SamsungGalaxyS6/

The iPhone 6 has a 4.7-inch display with a "2x" resolution of 1334 x 740 (326 ppi) while the iPhone 6 Plus has a 5.5-inch "3x" resolution of 1920 x 1080 (401 ppi). Both phones are said to offer higher contrast, better brightness, and improved white balance.

The 5.1 inch Super AMOLED display of the S5 is the most expensive component of the phone. The display has a price tag of $63. Compared to the display of Galaxy S4, S5’s display is cheaper by $12.

http://tech.firstpost.com/news-analysis/galaxy-s5-costs-samsung-256-to-build-reveals-ihs-teardown-221823.html

Lots of work to make a full panel. Design, Software. The value of silicon valley is not in making backplane technology but in making the free design. The design and talent in the Valley is too high. This is our first engagement, our first deliverable, to make one for Apple. HTC will absorb any extra AMOLED> It’s like making the full speaker. Even in terms of effort and experience for the people involved. That will give you the rich design experience, like building a chip. At the end of the day, they will like it.

They should encourage us with partnership. We learn from you too. When you design this thing it’s like you scan the TV. The number is very simple. What is the tdesign target, 7ms. How many px? 33m pixels. Pixel clock? If you just do one pixel at a time it’s some 7/33 nanoseconds. No CPU on earth can clock at that level so you have to access multiple pixels simultaneously. The question: how many? LTPS, you must access thousands/hundredsthousands pixels simultaneously. That number tgets reducsed for siog. The smaller number of pixels, the power consumption will be lower. And not all pixels need to change from on to off. The probability is associated with it. Added that in, and you build the mem cell from si instead of ltps, the stability of the cell becomes much greater. You’re not needing to engineer. The cell has to hold state. But if there is a leak in the transistor, we make less leaky transistors with silcon so it’ll hold state and no inadcvertant flips of the state so the pixel that is supposed to be off, stays off.

That’s why they’re interested. The industrial roadmap is low cost. So my guy iskilling me. “How can you keep costs low!” We can do the tricks necessary. He invented SOI. IN the 70s he was one of the first guys at Rockwell in Newport Beach. People had different R&D groups back then. Consolidation over time. Rockwell got absorbed by Harris. Waves of consolidation happen. Right now is one of those waves. Every 15 years or so. Back in the 70s and 80s.

We will have a unified. This the bio, this is the bio, this is the bio.

The engineering is very straightforward.

Because this is like VLSI, designing a chip, need to partner with SHARP and Panasonic. First we have to start a partnership. WE’ve already worked the numbers. They’ve published in 2013. 1.4million pixels. The dcurrent draw was 1.5 milliamps.

If you build a team of 100 people you are already ahead of Apple and Google at this point. Intermolecular guys are sitting there at Apple and Google including Raj. They are designing the panel. WE assemble these kids in Bangalore and the valley to be faster and deliver in getting the design.

1-2 target to 100 headcount. The problem with all this is that you know the specs and the targets. HOW DO YOU BEAT THE BIG COMPANIES FOR THESE PRIZES? Altera, for instance. 10,000 guys in the valley working on pieces of the same puzzle.

What AUO gets out of this: VANQUISH QUALCOMM ONCE AND ALL. Because QC is exiting anyway, business is bad. Only in display. In the imod and the Pixtronics side. That’s a lot of sunk money, their fab is sold to TSMC. What can TSMC want to do with that fab? They will sell it. They will convert it into a chip facility. TSMC is brother in arms with AUO on the display side. That’s good for them.

Once you get: once AUO says ok, Acer, Vixtron, all the people who make phones that don’t get branded. Not just phones laptops etc. They like it, they know.

500mw for 8K should be approximately 50% of the budget if you just use LTPS or IGZO.

We do some approximate scaling with a spreadsheet calculation or projection. The Sharp design is for 1900 x 1000 pixel form factor. When you ggo to 8k to 4k what does it look like? How does the power scale? If it scales that way on SiOG, how much would it scale if it were IGZO or LTPS? The expectation is that ti would be half. That’s in our spreadsheet.

You build the microcavity in a unit fashion? Per unit area. Cavity has higher surface area. The interface, junction, diode is higher because you’re putting into a cavity instad of straight. The surface area is the walls of the via over which you deposit the voled materials.

So the next thing on the slide, that’s going to be these guys. Between the pixel design and the architecture. Most of the people who are diesigning displays are not doing memory kind of design. If you do memory kind of design, if I have 1 to the billion ten to the power of nine, if I have a horizontal axis, a grid, row and column. If row size is 10 to the power of 4, and the colum is ten-5, so that sucks up a lot of power. So you need to use memory design to BISECT. We create blocks and blocks, chunks of small blocks that are hierarchically accessed. You keep the power low this way because you’re only using one cell at any one time. A three by three matrix, with control, would row-decode and column-decode. The size is very small in both cases. If you do that fine grained bisection architecture then yhou waste area. Each 3x3 chunk you’re building logic for acces. There is an optimium array for widgh and height w/r/t power. IN the display industry, they take whatever is the display size, they have one row decoder and one column decoder. The design technicqu is very archaic. A fallback form TV aera. Progressive or interlaced scan. Every bit on every pixel is accessed serially. Serial access wastes power. In order to acces the nth bit I have to got horuhg n-1 bit. A slightly refined display will bring power reductions from these. The latency calculation – their target is 7 milliseconds let’s say. Divide from the number of the columns on the matrix. For 8k it’s a minimum of 4k. IF I hav a target for vision persistence. 7ms/4000 is close to a megahertz, 1 microsecond. My roundtrip latency can be less than a few milliceoncs if I have an ondisplay clock. That’s what Sharp has. I want to come closer to the CPU clock. 3ghz is 1000 times. We can shoot for something in between 100 to 400. Ther are no issues for another 1-020 years. There’s no latency about the problem. The tiling of more pixels no matter what the device is now easy.

The tiling article is very interesting. TO tile bigger displays. So you build… That’s a little emore not what we want to do, because it isn’t momolithic. We aren’t fabricating one single die. That’s more for the Vue company. Prism company too. They’ll do the system level thing. WE focus on being altera/Xilinx. Micron. Fabricate the memory and run.

Now Semprius does this die transfer chip on glass thing. They did it by transfer then interconnect with thin film. Now whata re the size s of those areas, chips? What are they? Semprius is working on a bigger thing, four inch by three inch. SO the unit cell is 4x3” – that’s what they’re trying to do: video wall etc. I’m trying to take one entimeter and tile it. I want to tile this sie to this size, I don’t need to tile this to the table size, that’s low margin manufacturing. But they did demonstrate a lower led smartphone with that technique. I need an idea of the physical size of individual transistors. Just scale it by the area. So if Sharp is demonstrating ninemicrons, they’ll be 90 microns. It’s about 365 micron transistors. Because I have a new way of doing this which can batch transfer rather than individually. We are wnshooting for monolithical 3d installation. Just momolithic. 3d will come tnaturally. But our competition is monolithic 3d. Everybody, global foundries, all of them are working mo monolithic 3d. The size of the TSV is one micron, one micron Via, the hole. The object that drills through the suybstrate is going to be the same size as the unit circuit box. Then fine grained integration. When you have that, then you can do fine grained assembly of circuits. You then slap the wafers together and go. And you’re not integrating chips, youre integrating individual cirucits like an inverter. One via for 4000 transistors, not 10,000 transistors.

So, this is a wafer, we make these chips. Now you need to dice it. So your display, Microdisplay, is this one chip? Yes, one chip per Microdisplay. So then, you need to assemble it. And for that I need to do flip chip modeling on glass. What is the physical size/ I’m targeting 1cm square, as many pixels as I can pack in there. Or one inch, that’s ok> 2 ½ cm edge length? That’s a very good size.

Now the interconnect? That depends on – that’s the challenge, the electrical wires. There’s a tradeoff between performance and transparency. So you have to sacrifice the sheet resistence. The nano is 10 ohms per square. If you do that at 10 ohms per square you have to make smaller chips and you can’t do clocks (?) On chip resistance is high. If you want fully transparent one, it’s not abig deal, Applied and Cambri and all the spinoffs are ready ot go whenever the industry is ready.

I will end up with a lot of transparent areas. I’m looking at 10% surface occumpancy. The yield model is going to have philosophical divergence. The yield model we generally use are based on area assuming packaging densitiy is close to 100% . In the case of transparent displays you aren’t going to pack at 100%. You can build redundancy, technically, but theq question is: think about a scheme to use to break the access. The more pixels you pack… If pixel I is defective, and pixel 1=1 works, how do you make sure some random electrical noise doesn’t pturn the bad one on? That’s the fuseable leak. When we met the fremont fellow at SDI.

WE just take that applied AKT system. The ebeam breaks the fuses at the end of the line. Breaking the fuse disables the wrow and column access to the defective pixel. This is a design where everything has to work or else, every transistor ahas to work or there’s no reprieve? If you use large pixel size transistors that’s true, esp with no redudndancy. Advanced thechnology makes it happen. The fuse or antifuse process has to be extremely reliable. You can’t get regrowth of metallization. When you cut the line it’s cut. There’s no shorting of the line.

In the packaging geometries are very large. At IBM, they had at the surface of these TCM thermo module, they had these lines for repair. These were engineering change u. They tried to use a laser to cut a line but it created a big crater. Sriknath: there’ sre going to have soft repair. Electrical repair. Take this electrical gate oxide transistor. You use a transistor that controls the gate. This is a hypothetical pixel driver. This is a diode. This is a current mirror that sets the bias mirror. When we access this, when we wat to modulate the current o n the driver we put a pulse train into the transistor that moves the chrge and determines where the current flows. When we don’t want any thing to happen, we have this non volatile transistor. It’s a transistor that is stuck programmed on or off forever so that we break the connection to some of the node, a fuse and an anti fuse. E[prompt, electrically programmable read only memory, an EPROM. WE can now do some advanced EPROM arepair.

One to two years of feasibility onto product. You just need the right fab. Global might be that fab. We must check a few things. Global, TSMC, and if these guys take us,

It can be done if you have the Oculus design team here, it can be done in 6 months, it can be turned around on a dime. It just needs this team of a hundred people are so. Packaging, assembly, fab, ten people each for packaging, assembly, test. Fifty peple on the design side. So you can actually build an amazing VR display for 100 dollars per piece. The optics are what are actually critical. How do you get enough electroluminescence and enough light out of the pixel – that’s it, ready to go.

The reliability calculations are going to be more difficult. Dad’s worried about the mechanical reliability of the glass. You make holes in the galss that thin and deep, in a very thin glass. The water vapor transmission rate. Oxygen and water vabpor diffusion into te glass must be kept down, that limits the packing nature of how many pixels you can reliably make. That’s why Microdisplay MCM is better. If you’ve got defective MCMs you can repair them. Instead of building a monolithic 4x3”, and through it out if it doesn’t pass the water vapor test, that’s a bad idea. If it is stuck, then you waste some $30 worth of material because you decided to go that size. Anything you fab on a large scale has that problem. ON a microscale the situation is better with better economicsl. The assembly yiled is usually much higher. You make the bricks, keep the bricks smaller, and then you build the wall.

Look at the tiling patent? What is butting? Define butting?

The way the OLED industry is doing it, they put this chip on glass, one chip on glass like this, and then they put another one in a socket or some kind of thing where it’s slightly deeper than tiling the thing so that one OLED Microdisplay is here and one here, at a different depth. And then this is all glass. So that when the light emission comes through even if there’s overlap it’s in a zone where the top light is emitting and the light from the bottom is blocked. Very crazy scheme. IT’s not a good quality thing but it’ll work reasonably for large pixel sizes. With small pixels quality issues but with big pixels you can get away with it. So we are thrusting to small pixel sizes. Now tiling will be a huge technical challenge. How do you keep the quality of light output and the cross talk noise under control optically. Lots ot work on!

Let’s assess the packaging problem. It’ll look in plan view as butting each other. What is the Io density? You can use Rens tool. YO’re only talking about 11 million transistors. Per chip you’re talking about twenty pins. I have a way of attaching the. There’s like four or five per inch, six worth case. You need to have those tabs interlock at six joints per side. The tiling, instead of doing it like this, if we say wwe have six leads per edge, then we do it this way. We create a joint here. We kind of have a rescess and a land kind of structure to do that joint that’s in between. Instead of a ball and socket you can also have leads at different Z heights. Maybe flip chip on these things? The lead count is not that high. You can just do edge. Flip chip is easy and batchy, so Srikanth says go for it. Place and refold.

As long as all the structures can withstand… the problem is that now you have to think about underbound metallization, reliability of the underfulll, stress delamination. Is that a big topic you want to take on? How many times do you have to do individual bonds? There are a lot of bonds. 12x25 is 400 unit bonds. If you really push the density it becomes more complicated. For 400 stitches are fine. It’s done at the wafer stage and it’s not a separate operation, you just put assemble and reflow. This is Andy’s contribution. It allows you to rework. If the chip is not good you can take it out and do it over. All those decisions Srikanth wants to avoid on his onw. Just rying to get that underbound metallurgy is a huge hard thing, but Andy knows how to do it.

It’s called lead free solder transition. Non leaded solder is the way forward. Nickel cobalt.

I actually rpfer kind of glass reflow, ITO reflow, then it’s transparent. We do reflow of boro phosop silicate glass for dielectric. VTSG is 800. Interesting.

A-si buys you nothing. If they want to put a photodiode on it, then that’s good, but you can just put a single crystal and you’re fine. The gate being a-si, how does it matter, I have molybdenum gate… How do you tune VT? A-Si as a transistor??/ If I have the transistor as a-Si, I’m saying that the only thing that’s amorphous is the a-si gate. The channel is crystalline si. If you put the channel as a-si, you get ultra low cost and also leakage current low. Also the leakage is very different very little. Maximum of one order of magnitude, 1on, ioff. The bang you get on the transistor, and the reliability is so high, it doesn’t make sense to use the a-si transsitor that’s given to you by the fab. They’ll all give you the option to use an a-si transistor, Srikanth says just rhouw it out and use a regular c-si transistor. They can do a l little more cost optimization. They can only give you one p channel transistor for the driver. The pi channel is all crystalline sislicon. You save mass cost. To me at 15 dollars per mask layer, this stuff is important for LG’s 85” telelvision. That much aggressive cost reduction isn’t key for microdisplays. Keep it simple is better. Mask reduction will come 20 years later. That’s very aggressive. They’re tyring to do 50-7 masks, these tiawanese guys, is it key to be in this game? If you’re making the backplanes then you are doing an analogue of LTPS. Then yeahh. IT depends on the price point of the backplane for the television.,

I don’t want to be in that business, but that may be our first product. We want apple to use our backplane. They’re tinking of LTPS today.

Luminous output. That’s to be maximized. Knobs to recover the light. The performance you can turn it up by sending more current? Well the lifetime of the device will go down. We want ot have a platform where we use the tricks that keep us scalable.

When Apple switches to AMOLED, then 8K will probably be one of the criteria.

1. We need to get plugged into this ecosystem somehow.
2. Whatever we can contribute we’re happy to work with them.
3. They have $179m to spend a. Two investors participated in funding this b. They have working prototypes of the world’s thinnest and smallest scale displays c. These guys are from IBM d. ROYOLE. On Fremont BLVD.
   i. Let’s go talk to ROYOLE! e. Take a small presentation and go there meet with them today.
4. All we say is “you have an amazing supply chain built up already.” a. You need some design companies to bu8ild with you to make products. WE can do all this grunt work and you take the glory. b. Design, test, software, opening markets in India etc. c. These guys are major players. KKR etc.
5. You have to think ONE COMPANY. a. You need everything. b. At the end of the day without design and without product you can’t do anything.
6. Sanjay and I and a few other people can take care of the front end. a. Andy and Sarko can handle the difficult backend. b. It’s hard because it involves all this negotiation stuff, budgeting, people, legal crap etc. c. Nothing to do with getting a chip or a software out.

You would mention ROYOLE as a way to get to what?

1. Eric may know about ROYOLE and Aneesh knows about them as well.
2. Bill Lu is 33 and was working for IBM and Global Foundries with patents.
3. He and his friends were only five guys until recently.
4. They have tremendous amount of support from China. a. They have some real political clout there somehow.
5. Bill is Chinese.

Is this platform of Single Crystal Silicon useful to ROYOLE? They are not yet using single crystal and are able to achieve good stuff. They can collaborate with you on the full system and we do the design. This will help them, but do they have a supply of single crystal? This fact they are building something means they have factories in china pumping these out at the prototype level.

You have to have the credibility to get the money. Only demonstrating a prototype will get you the money. AUO can demonstrate the prototype with our technology.

We’ve been trying to do this for two years. We’ve looked at it and we think you guys are incredible and we want to build with you.

Everybody has forgotten about Single-Crystal Silicon-On-Glass, as if it never existed, and therefore never will. Now, if we can disabuse them of this notion that creates a possibility for many other devices.

It’s possible, economical, and we are doing it today for the GaN thing (we just did it last month even in large format according to Sarko).

Let’s say we go to Intel for money. The possibility now exists to develop a whole list of products in that medium. Give me a list of products, that might attract VC attention, and we can go to Intel Capital.

We are here to enable innovation across the device landscape.

Intel is a leader in semiconductor technology. They may not have thought about the possibilities for this new clear semiconductor technology. This is right in the pocket for the dreamers of the Valley. We can outdream anybody with the platform we want to build.

Intel’s idea is to develop technologies based on other people’s equipment. They use other people’s equipment to make the best products. Sometimes we say we need equipment for this and this but most of the time they survey what equipment is available to make this dream product.

We can sell this out to those guys, let them back and forth for a week. They are doing this at a home computer. In this case it’s early enough that it attracts attention; it’s not a specific product. To counter it, it is vast possibilities to attract attention of Intel. Especially when we show these wafers in person to them. They will also be surprised it can be done. Also AMD. But Intel has the money to invest in R&D. In this case they will see far into the future and say: let us be in this space. Let us patent everything that is possible for single-crystal silicon on glass so that they will dominate in this area.

Since 2007 nobody has touched this stuff. Nobody has talked about single crystal silicon on glass for some strange set of reasons. They can create near-CMOS type of devices; it’s already been show.

CMOS is complimentary metal oxide. CMOS type of devices. Memory chips and even logic and memory chips. This is what put jobs in jeopardy at IBM. We were fist building computer logic chips on bipolar devices or larger in physical size, each transistor was larger. It gave out a lot of heat, it takes a lot of current. Whereas CMOS enabled the shrinking of the devices, packing more of them on the wafer. It was tremendously disruptive. What IBM was doing on 300 or 400 chips, they would shrink it down to 3 chips. They did not need our 50 layer packages anymore. The thing is so compact.

CMOS made packaging obsolete, this complex packaging. Now let’s pay it back to them.

You peel off layers and layers and get to the simple truth. You can give specific advice books. If you make it simple and simple you can lead by pri9inciple. This applies to all life situations.

Think of this.

eMagin sowed us a fantastic device on a single silicon chip. That by nature is a very small chip. If you present Intel that you can create that device on this entire wafer as a chip, what could it be? I don’t know. Maybe it’s not needed. But the possibility exists. That’s why we were careful not to talk to eMagin what we were doing. They were making a CMOS type of device on a single chip. A CMOS type of device means a very high-density transistor. Now, CMOS is at very high level of integration already. But if they can do this integration on a large silicon substrate whether they dice it or not it’s still amazing. This is what we should be doing.

Corning has offices here in Silicon Valley too, but since they are east coast they should not have the vision to make it a next generation silicon wafer for other things. They just want to sell glass. They want pioneers like us to take the ball and run with it. The SOI made a lot of new devices that silicon itself could not because silicon is very thin but it’s carried on a silicon wafer. We’ve created another SOI. This is thin silicon on glass and for some application the glass is a better dielectric, that means not a conductor (the opposite of a conductor, aka an insulator).

It’s this idea of a clear semiconductor that opens up new opportunities in manufacturing. The semiconductor is the screen.

Regular silicon wafers are at least 700 microns thick. This is a chip that I cut out of a silicon wafer. They make a transistor, especially CMOS transistors. They put a very thin oxide there, like an insulator. They open a window in the oxide, two windows in the oxide, and diffuse phosphorous here and diffuse boron here. So it’s making an ion plus and ion negative. And then they put a source and drain. And then they put electrodes; the source the gain and the gate. So depending on the voltage and the source and the drain it acts like a throttle so they can switch it on and off. For memory devices, it’s just on and off.

For some other devices, the level of the current is also important, in which case it’s more than just memory; it can also be a current driving device, or a switch.

As the devices are coming closer and closer and the current was becoming higher and higher, they had to make innovations to make this work better. So here, the source and drain is still in a semiconductor. So what would happen is there is leakage current between this and this even where there is not supposed to be any current flowing because it’s immersed in the semiconductor.

Trench isolation! One IBM E Fishkill guy said I want to prevent the current leakage so what I’ll do is dig a trench here so that there is no current flowing, it’s like a virtual wall. He took out the semiconductor from out of there. Trench isolation. That gave them one or two generations of further miniaturization. Soon that trench isolation became NOT GOOD ENOUGH. They literally dug out the silicon from around here. You now have the source and drain but you still have, there’s a lot of silicon where it would diffuse although you’ve cut down most of it. Even if you can make the trench deep enough you still have some silicon area that transported the current. So IBM invented the SOI first but SOITECH made it big.

In SOI what happens is what I need is a very thin layer of silicon for the device. This is of single crystal silicon to make my gate, drain and source. Ideally I would have an insulator right underneath. There is no current pulling now. And then I will have silicon there for just a support. The rest of the silicon is just a support. So when they make a SOI wafer it’s silicon on insulator. They do the same thing we do for the SiOG - implant hydrogen. They exfoliate onto a silicon wafer as a support because it’s expansion matched and they don’t have to worry about the cost.

The insulator is a very thin oxide. They can thermally grow this insulator. That’s good enough to enable 3 to 5 generations of reduction in size of the devices, the memories.

So SOITECH became famous for making SOI wafers by this process. So all the devices they can make on SOI they can also make on silicon-on-glass. So here, GLASS IS A MUCH BETTER INSULATOR. So here, we don’t even have a semiconductor at the bottom. Even the support substrate itself is an insulator. So that is basically what these guys are saying: we can do ALL the devices that they today make on SOI on silicon on glass. The quality may be low because the glass is supposed to give some impurities in the silicon. But if it’s a generation or two behind, the silicon integration is still acceptable. As long as you can do it, it’ll be very useful and valuable.

In glass, you can also combine it with amorphous silicon. That’s a new angle. The root idea can do many different paths. But if you catch the root idea later on, you get a lot of good products but you exclude a lot of other things. But going back to the root idea, you have opened up a lot of possibilities, which can obviously be seen. It needs more development, but everything in that book on silicon wafers can be done on ours. It’s the same single crystal silicon.

They may argue that silicon on glass may not be as pristine on SOI, and we compromise on that, but the level of integration doubles.

What would someone say at Intel Capital of they saw this?

Brian Shieh would be very intrigued. We never thought any of this would be possible. We are doing it and we have the expertise. We have a duty to bring it back.

We are the only experts. We have the only people with expertise to make this routinely and the knowledge that it will be useful. People have forgotten. We can begin anew because we have a long memory.

We also discovered a Microsoft link the other day. Here in the Valley they are doing advanced displays.

Intel will react very favorably because this is something disruptive in semiconductors that was not on their radar.

First, you have a lot of expertise in making very great devices on silicon. Can we leverage that?

For some people this may be a regressive step because already they are doing it on silicon and silicon is the highest grade silicon and the best devices. Some people will see it as a regressive step. For other people it may be very groundbreaking step because if we can apply what we have done on silicon to glass even though at not the level of sophistication of silicon we can open up the possibility of other devices: cheaper and larger. And because of the transparence of the glass it opens up a whole new ballgame for us. If they are a progressive company as we know they are they will look at it as an opportunity. Here it is. You can make it on whatever size of panels that you need and very economically too. That’s basically the point they will gain from meeting with us. This is sufficiently thought provoking to them that they’d rather be there first than let anyone else. So let’s let these guys make product ideas and make an appointment with Intel Capital.

We have this for displays. This would still be a valid area for that technology. On the other hand you guys are progressive enough to fund this early startup to bring our players here. Dream big and other possibilities open up.

So, for them, what is the prototype? They don’t need a device because they know how to make it themselves. SO if you just showed that wafer to them, that’s the prototype. The possibilities are endless. It opens up a lot of possibilities. If these people give us an idea before that, some types of devices for system-on-glass…

System of glass means you have both the drivers and the logic and the memory on the same system. Usually the memory chip is a different chip, logic is a different chip… so you integrated it outside on the board. But if you say it’s a SYSTEM ON GLASS where the cost is mostly the glass because silicon is cheap… Let them give us some product ideas. We have one already on display devices for smartphones and other product ideas. We are a blank slate and this is a new continent for you to populate. A new type of land, too, which is transparent, cheap and amazingly versatile. We have a team that is able to deliver this within a short time frame with you.

They must go from unaware to high-priority. NOBODY IS AWARE OF THIS. If we don’t get your money nobody else will bring this to you and it’ll be dead to you forever while you watch the future be funded by someone else.

Field stitching. With patterned exfoliation the physical wafer will be removed only keeping the bits we need. After wafer is selectively exfoliated there will not be a physical obstruction because only bits of Si are left. Now second wafer can be perfectly aligned. No physical obstruction is there from the first wafer. We use the exfoliation method instead of embedding silicon into a medium to some depth. A much wider field than an area of a wafer can be created with our novel approach. We choose to use indexing to create wide fields without boundaries, field stitching. Perfect alignment if you can repeat that pattern accurately as if unbroken and this index makes this possible. All they need are little bits of Si to create the driver TFTs. After exfoliation is done, Sarko wafer, we only keep about ten percent of the Si. You put a photoresist to protect those areas. All else is exposed to the HF agent. In patterned exfoliation you use a photoresist to block off the areas during implantation. Only open areas get implanted and when You exfoliate it on the glass only those protected areas are left. A continuous pattern is possible because you can place the next wafer accurately with registration marks. Without the first wafer obstructing the placement because it has been removed. Same periodicity between the boundaries. Patterned makes it happen and a very good reason to put it in. By indexing you can avoid butting. Selective lets you overlap the area. Use fiduciary alignment path. This makes the two paths coincide and you now can stitch a large field. Islands of silicon to form the TFTs, but his takes spheres and convolution, polish etc. we just use SiOG everywhere. Patent this. Sarko pattern gives an alley between wafers. These alleys can overlap. One wafer at a time with an alignment fiducial you can overlap the two. Now you can do exfoliated wafers with any size you like. As long as you know exactly where the first wafer left polka dot you can save a registration mark. The second wafer is now aligned with that mark. The registration Mark is removed and the second wafer can intrude into the gap that used to be this. You can overlap because you do it one wafer at a time. The second wafer can now align. One by one they align. Tedious but possible. Indexing makes it possible. Polka dots. You know exactly where you left the first wafer because of the index. So the index lets you precisely refer and align. Simultaneously exfoliating doesn't allow alignment. But sequentially you can align the fields. Wider wafers mean wider devices like a TV. There are four individual wafers in sarko world. But now merge these into an area together then no limits. OLED tvs cost $25000 now. This will bring them down to $5000.