Gallium nitride (GaN) is often regarded more or less as the younger brother of gallium arsenide (GaAs), and to some extent this is an accurate view. Lately, GaN has been receiving a great deal of attention, for the most part because its strong points - handling high frequencies, high power levels and higher operational linearity - are required by technologies that are now, or will soon become, significant economically.

The market for GaN devices can be divided into two main sectors: LEDs, where GaN enables much higher efficiency in green, blue and ultraviolet applications; and communication devices, where power and linearity become paramount. GaN has been used in LEDs for some years, but its application in volume to solving communication problems is really just getting under way. Two of the most important applications are in mobile telephone base stations and in military radar systems. In particular, the military sees a vital role for GaN in X-band radar systems. This is the high-end application area that GaN should excel in.

Although the need for GaN devices is motivating a great deal of exciting research and development, the volume of GaN devices being sold into all markets will, in the next few years, amount to no more than a small fraction of the volume of GaAs devices sold. At the moment, there is no reason to suppose that this volume relationship will change much if one looks ahead five or even ten years. As exciting as GaN is, there are simply many more mobile phone handsets and satellite television receivers that use GaAs chips.

One of the most active areas of research and development in GaN is the matter of native substrates for GaN. At least six different substrate materials are currently being used, at least experimentally (and in most cases commercially), for GaN. The reason for such a diversity of substrates is that there are no GaN ingots, as there are ingots of silicon. If GaN is melted to the required very high temperature in an attempt to grow a crystal of the material, the liquid simply dissociates into gallium and nitrogen.

There are, however, GaN substrates onto which GaN is epitaxially grown. The substrates themselves are grown, and then sliced into wafers. Most GaN-related epitaxial growth processes are limited in thickness (the active layer of GaN on a wafer of any material is generally 1 to 2 microns), but one firm, Kyma, has succeeded in growing GaN substrates that reach 1-centimetre in thickness.

At the moment, the native substrates in use for GaN, for both LED and high-frequency, high-power applications, include bulk GaN, diamond, silicon carbide, sapphire, aluminium nitride, and silicon. Additional substrates, such as AlN for LED substrates, are beginning to look for market share. The governing factors in the selection of the substrate type for a given application include the degree of lattice mismatch between the active GaN layer and the substrate, the thermal conductivity of the substrate, the difference in coefficient of thermal expansion between the substrate and the epitaxial layer, and the overall cost of the substrate.

MACOM expects a bifurcation in the GaN supply chain for low volume applications. Cost-sensitive applications will go the path of 8" GaN on Si. At the same time, capital-lite fabs will service diverse, low-volume applications with specialty GaN processes.

It’s fair to expect a plethora of technology variants for niche applications, including GaN on SiC.GaN on SiC will remain the purview of low-volume, niche applications due to the inherent cost structure of substrate material. Fundamentally, at a physics level, SiC boules grow 200X to 300X slower than silicon. The cost of producing substrates – notably capital depreciation and energy consumption during material growth – scales proportionally to production time. Thus, GaN on SiC will remain perpetually higher cost and thus prohibitive for mainstream commercial use. GaN on SiC production for the highest power density and defense applications will play to the strength of capital-lite fabs that aren't exposed to the technology transition in handsets. Such factories can support a high diversity of relatively low-volume programs, and their capital structure can ensure long-term supply without facing consolidation as handset production transitions to silicon.

Introduction

MACOM has assumed a leadership role in driving the commercialization of GaN into mainstream applications. Offering the RF and microwave industry’s only portfolio of both GaN on Si and GaN on SiC products spanning a wide range of package options for pulsed and continuous wave applications, we have firmly established ourselves as leaders across all GaN variants and all end market applications.

Performance

Regarding the maturation of GaN technology, we know today that GaN on Si delivers minimally 8X the raw power density of incumbent GaAs technology, while boosting efficiency from the mid 40% to up to 70%. We believe it can do this at minimally 2 to 3X lower cost than GaAs at maturity in 6” handset fabs.

Commercialization

GaN technology is now making the transition from specialized, government funded technology to high volume commercial mainstay. By leveraging the scale volume of the silicon industry, which is two orders of magnitude greater than even the GaAs handset market, we’ll soon be able to leverage GaN for cost-sensitive applications. At maturity, we believe that GaN on Si will benefit from silicon cost structures that are 3X lower than today’s highest volume GaAs and 100X lower cost than today’s GaN on SiC technology.

One of the more intriguing substrates for GaN is silicon itself. Nitronex (Raleigh NC) has patented the process that epitaxially grows 2 microns of GaN on a standard silicon wafer. Silicon is not as efficient in removing heat as diamond or SiC, but it is a thoroughly characterized material that many customers feel comfortable working with.

The GaN-on-silicon are primarily used in AlGaN/GaN HEMT devices and other high-power, high-frequency applications, company director Dr. Eddie Piner observes, and not so much in optoelectronic devices. After front-side processing, the wafer is flipped over and thinned down from its original 500 to 525 microns to improve thermal performance, he says. Nitronex recently announced a new series of devices grown on 150-micron (6 mil) silicon. He adds, “We have work under way for some other products in which, based on the modelling and thermal characteristics, dictate that we need to get down to 4 mil [100 microns]. We're well on our way to finishing up that work, and those products are probably middle of next year time frame before they're really needed.”

Nitronex currently produces 100 mm (4-inch) wafers, and plans 150 mm (6-inch) wafers for 2007. “We have a number of people who are interested in that size, primarily from the perspective of the GaAs line…that they're currently running,” says Piner. “It's not necessarily being driven by the need for the larger area for cost reasons yet.”

Technically, he notes, there are no impediments to moving to 150 micron wafers. Silicon substrates are readily available, and there are no quality problems in depositing GaN onto the larger wafers.

One obstacle was the limited number of growth chambers used to perform the epitaxial deposition. But new growth chambers have recently been demonstrated that will accommodate 6-inch wafers and GaN. The same chambers are used for performing deposition on 2-inch sapphire or silicon carbide wafers.

“What they're interested in is not really 6-inch GaN, but really in how many 2-inch sapphire or SiC wafers they can fit in a chamber for their LED customers,” Dr. Piner says. “And in that platform instead of loading six 6-inch wafers, you basically pop out the platter that holds the 6-inch wafer and you put in a platter that holds seven 2-inch wafers. Of course you have six of those [platters], so that's 42 2-inch wafers you can grow at a pop.”

The transition to larger wafers will not be free from problems, he adds. “There's still a transfer qualification process that would have to go through to transfer the silicon process that we're running now over to that platform, but it's an engineering activity - it's not a science experiment. So the limitation is the commercial pool for that many wafers. If you do the math, and we run into the 6×6 configuration, typical turn-around times are 4 to 6 hours - let's say 6 hours to be conservative, so that's 24 wafers a day.”

He notes that there are some other high-volume markets that are also interested in GaN. Optoelectronics makers are an obvious market. Dr. Piner thinks that these markets will have an expanding need for GaN on silicon in the form of 6-inch wafers.

“When that happens is really a question of market timing, and the need to get the price structure significantly lower,” he says. “That's a least one order of magnitude lower cost than what people are seeing today, and of course much higher volumes.”

GaN microelectronics is at the threshold of commercialization, however, there are still significant reliability challenges to be addressed.

While GaN device performance is often already at an acceptable level, device reliability is often not adequate to accept the higher risk involved with this new technology for real-life applications, when compared to traditional technologies such as GaAs.

For example, applications in satellites require high reliability as replacing a device once in operation would be costly, and is therefore presently not a realistic option both from a technical and from an insurance viewpoint, unless high enough reliability can be demonstrated and certified.

Similarly applications in safety and in security critical applications have stringent reliability requirements.

Prime research demands therefore lie in the area of GaN microelectronics reliability.

Typically device failure is a combined effect of excessive device temperature and high electrical field in a device.

Device failure rates can vary up to exponentially with device temperature, dependent on failure mechanism.

Mapping of temperature in the active area of a device is therefore not only key for the optimization of device performance but also one important aspect to tackling device reliability.

Traditional thermal imaging techniques such as IR thermography, however, lack the micron/sub-micron spatial resolution needed to measure accurately device peak temperature in many of today’s devices.

Device heating for example in an AlGaN/GaN HFET occurs in the source-drain device opening, predominantly within a 0.5–1 μm size region near to the gate contact.

When measured using IR thermography device temperatures are typically averaged over a several micrometer size area, and therefore device peak temperature is significantly underestimated.

This results ultimately in an underestimation of potential device failure rates. Improved new thermography approaches for accurate temperature determination are needed.

Detailed knowledge of the device temperature is also essential for device lifetime predictions based on accelerated lifetime testing data.

Furthermore, many devices are operated in pulsed mode. Probing of their thermal characteristics often requires assessing temperature with submicrosecond time resolution. These time scales, however, are not easily accessible with traditional thermograph

Infineon and Panasonic Will Establish Dual Sourcing for Normally-Off 600V GaN Power Devices

Munich, Germany, and Osaka, Japan – March 10, 2015 – Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) and Panasonic Corporation (TSE: 6752) have announced an agreement under which both companies will jointly develop

Gallium nitride (GaN) devices based on Panasonic’s normally-off (enhancement mode) GaN on silicon transistor structure integrated into Infineon’s surface-mounted device (SMD) packages.

In this context Panasonic has provided Infineon with a license of its normally-off GaN transistor structure.

This agreement will enable each company to manufacture high performing GaN devices.

Customers will have the added advantage of having two possible sources for compatible packaged GaN power switches: a setup not available for any other GaN on silicon device so far.

Both parties have agreed not to disclose any further details of the contract.

For the first time the companies will showcase samples of a 600V 70mΩ device in a DSO (Dual Small Outline) package at the trade show

Applied Power Electronics Conference and Exposition (APEC), which will be held in Charlotte, North Carolina, March 15-19, 2015.

GaN on silicon has been receiving significant attention as one of the next compound semiconductor technologies that will on the one hand enable high power density and therefore a smaller footprint (e.g., for power supplies and adapters), and on the other hand serve as a major key for energy efficiency improvement.

In general, power devices based on GaN on silicon technology can be used in a wide range of fields, from high voltage industrial applications such as power supplies in server farms (a potential application of the showcased 600V GaN device) to low voltage applications such as DC-DC conversion (e.g., in high-end consumer goods).

According to an IHS market research report the GaN on silicon related market for power semiconductors is expected to grow with a compound annual growth rate (CAGR) of more than 50%, leading to an expansion of volume from US$15 million in 2014 to US$800 million by 2023.

“Infineon is committed to serve its customers with a broad best-in-class product and technology portfolio including reliable power devices based on Gallium nitride. We are convinced that enhancement mode GaN on silicon switches, together with our corresponding driver and optimized driving scheme, will provide high value to our customers, while the dual sourcing concept will help them manage and stabilize their supply chains,” stated Andreas Urschitz, President of the Power Management & Multimarket Division of Infineon Technologies AG.

“Panasonic developed its normally-off GaN power technology which has a simple configuration and easy-to control dynamics, by making full use of its compound semiconductor experience. We expect to accelerate the expansion of GaN power devices by licensing our normally-off GaN transistor structure out of our GaN power technology to Infineon. We will continuously contribute to solutions for consumer requests by innovating our normally-off GaN technology”, said Toru Nishida, president of Panasonic Semiconductor Solutions Co. Ltd.

GaN – in comparison to the best silicon alternative – will enable higher power density through the ability to switch at high frequencies, as well as achieving highest efficiency through novel topologies such as the totem pole PFC. Higher frequency operation can improve power density by shrinking the size of passive components as well as saving energy on cooling the whole system.

GaN switch performance features low charge and excellent dynamic performance in reverse conduction compared to Silicon FET options, enabling more efficient operation in today´s applications at existing frequencies.

International Rectifier has developed cascode GaN switches with low-voltage FETs while Infineon has developed enhancement mode HEMT devices in partnership with Panasonic. Customers can now leverage the specific advantages of these GaN technologies versus Silicon by application/system. At the same time, Infineon is committed to developing the necessary Surface Mount Device (SMD) packages and ICs to fully exploit the superior performance of GaN.

The Department of Energy funds Dad's GaN experiments within one month.

Power supply designs can benefit from GaN transistors now using existing controllers and drivers for LLC and ZVS Phase-Shifted Full-Bridge topologies, operating efficiently at frequencies extending beyond the reach of superjunction.

Look for advanced controllers for totem-pole bridgeless PFC and even higher frequency resonant and soft-switching topologies to compliment a broadening portfolio of GaN transistors in the future.

By combining these topologies with state-of-the-art drivers and GaN transistors, tomorrow’s power supplies will be able to take full advantage of the efficiency and density gains made possible by high voltage GaN transistors.

High performance power supplies today are already very efficient.

For at least two years, “Titanium” efficiency server power supplies have been announced with greater than 96 percent overall energy efficiency at half load (per 80 PLUS®* standards).

These power supplies achieve this high efficiency level using today’s available technology including high performance Si FETs and SiC Schottky diodes.

So what comes next?

With several companies announcing the availability of GaN on Si 600-650 V transistors, how will these new devices take power supplies to even higher levels of efficiency, and density?

To begin, consider the limitations of existing Silicon FET technology, and what power supply designers would want in a more ideal switching device.

Controlling conduction loss is straightforward: a larger area FET or several FETs in parallel will reduce effective RDS(on) to negligible levels.

But there is of course a tradeoff here.

More FETs also means more capacitance (and, therefore, charge), thus increasing frequency-dependent switching losses.

So for a given frequency range, power supply designers must balance conduction and switching losses to achieve the overall lowest total loss.

Moreover, the dynamic characteristics of a FET body diode have a significant impact on frequency-dependent losses in certain topologies.

This is where new technologies like GaN can add value.

For a given RDS(on), GaN switches have lower output charge Qoss, lower gate charge Qg, and vastly lower reverse-recovery charge Qrr,

than the best available Silicon FETs.

GaN devices have a much more linear charge versus voltage characteristic

than superjunction FETs (superjunction is the dominant high-voltage FET technology used in power supplies today).

The linearity of Qoss plays a key role in reducing deadtime and, therefore, enabling high efficiency at high frequencies.

The new breed of GaN devices are High Electron Mobility Transistors (HEMTs), which have been described in numerous publications recently.

To be cost-effective, HEMTs are manufactured on Silicon substrates, rather than Silicon Carbide or pure GaN which are both easier, but considerably more expensive.

HEMTs are lateral devices that can be manufactured as either enhancement or depletion-mode transistors.

For power electronic designers, a normally-off power switch (meaning the FET is off when the gate voltage is zero) is much preferred over a normally-on device, even if the normallyon device could provide some additional performance.

This is because normally-on devices make it challenging to control current during power-up and power-down for example, requiring a master enable switch or a pre-bias arrangement to make sure the normally-on devices don’t turn-on randomly when the control circuit is booting-up or powering-down.

Early 600 V GaN HEMTs developed for power electronics were depletion-mode devices.

To solve the normally-on issue, the depletion-mode HEMT was combined with a low-voltage Silicon MOSFET to form a normally-off hybrid device known as a GaN cascode.

Enhancementmode GaN HEMTs at 600 V (which are intrinsically normally-off) were perhaps more challenging to develop, but are also now just becoming available on the market.

Enhancement-mode and cascode are two different approaches to providing a high performance 600 V normally-off GaNbased switch.

While there are differences between the two devices (mainly in the gate drive circuit and the reverse conduction characteristic), both devices provide vastly improved “body diode” performance Qrr, and significantly lower Qoss and Qg compared to the best available Silicon FETs with similar voltage and RDS(on) ratings.

The key attributes of these devices are outlined in the comparison chart.

The data is gathered from recently published articles, papers and datasheets, and normalized to 100 mΩ typical RDS(on) assuming R x Q product is constant.

It is not necessarily representative of a particular device, but shows the performance trends between these technology platforms from multiple vendors.

How do these attributes translate into a benefit for power supplies?

The answer is that it depends strongly on the topology.

For example, consider traditional boost PFC, which is the most common PFC circuit used today for server power supplies.

This is a unipolar topology, so the FET only conducts current in the forward direction – the body-diode is never used.

Since this topology is mostly operated below 100 kHz, the gate charge losses are relatively low, so any benefit in Qg is minimal.

The two dominant parameters that most affect efficiency are RDS(on) for conduction losses, and the energy dissipated each switching cycle due to the discharge of Qoss when the FET turns on (Eoss).

This is where things get confusing: even though the Qoss of the GaN HEMT is significantly lower that the best superjunction, the Eoss (the energy stored in Coss) difference between superjunction and GaN is much smaller.

The lowest Eoss superjunction can be better than cascode GaN, but not as good as enhancementmode GaN.

This paradox occurs because the bulk of the charge stored in superjunction is injected at low voltage (<50 V).

Above this, from 50 V to 400 V, the effective charge is lower, but the energy is much higher since C (V) dE = ——— dV2 (1) 2 (note the V2 term and the value of C is a function of V).

As a result, even though the charge Qoss at 400 V is 5 to 10x lower for GaN than SJ, the energy difference is much smaller: the best superjunction is better than cascode GaN and within 15 % of enhancement-mode GaN.

The net result is this: if you simply drop-in the same RDS(on) GaN switch into a highperformance superjunction socket like this PFC example, the overall efficiency change is barely measurable.

To get to higher levels of efficiency, one must look more closely at how power loss is distributed in each topology.

The main source of loss in traditional boost circuit is not typically from the switch – loss is dominated by the input bridge rectifier which always contributes two (2) diode drops over the entire line cycle.

To utilize the full benefit that GaN transistors offer, consider instead the totem-pole bridgeless boost circuit shown in Figure 3.

In this topology, there is no input bridge rectifier, and, therefore, no diode drops (except 1 briefly during deadtime).

The low-frequency half-bridge on the right flips the polarity of the line every half-cycle, so switching loss is negligible, only conduction loss matters (this can, therefore, be low cost superjunction).

The half-bridge on the left operates at high frequency (typically Continuous Conduction Mode CCM in the 50 – 100 kHz range), with one transistor serving as the boost switch, and the other as the synchronous rectifier – and they swap roles each half-cycle.

Besides eliminating all diode voltage drops, this topology has the additional advantage that it can be operated in CCM, CrCM, DCM and even ZVS mode, which enables much higher operating frequency while maintaining outstanding efficiency.

The totem-pole bridgeless boost is not a new topology; it has been around for many years.

But until now, the high performance FETs (with low or zero Qrr) have not been available to enable practical implementation.

Now with GaN transistors in this topology, several papers have recently reported energy efficiency of the PFC stage exceeding 99 % at standard operating frequencies in CCM.

Moreover, a recent CPES presentation from Virginia Tech demonstrated this topology operating in ZVS mode into the MHz range, also exceeding 99 % peak efficiency.

This level of performance is quite compelling, and will clearly drive development in the next generation of high performance, high density power supplies using GaN transistors.

The isolated DC/DC stage in power supplies can similarly benefit from GaN transistors.

But just like the PFC example above, the benefit is not fully realized by simply dropping a GaN transistor into a FET socket in an existing power supply design, especially in hard-switching unipolar topologies where superjunction already does very well (Flyback, twotransistor forward).

The topology, control strategy, magnetics, and operating frequency all need to be considered in the overall design when optimizing for GaN devices.

GaN is particularly well-suited for soft-switching and resonant topologies like LLC half and full-bridge, and ZVS phaseshifted full-bridge.

The low charge of GaN devices reduces the circulating currents necessary to achieve soft switching, reduces deadtime and therefore rms currents, and reduces gate drive power, while still enabling efficient operation at higher frequencies with smaller passive components.